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74LVQ74 Low Voltage Dual D-Type Positive Edge-Triggered Flip-Flop
May 1998
74LVQ74 Low Voltage Dual D-Type Positive Edge-Triggered Flip-Flop
General Description
The LVQ74 is a dual D-type flip-flop with Asynchronous Clear and Set inputs and complementary (Q, Q) outputs. Information at the input is transferred to the outputs on the positive edge of the clock pulse. Clock triggering occurs at a voltage level of the clock pulse and is not directly related to the transition time of the positive-going pulse. After the Clock Pulse input threshold voltage has been passed, the Data input is locked out and information present will not be transferred to the outputs until the next rising edge of the Clock Pulse input. Asynchronous Inputs: LOW input to SD (Set) sets Q to HIGH level LOW input to CD (Clear) sets Q to LOW level Clear and Set are independent of clock Simultaneous LOW on CD and SD makes both Q and Q HIGH
Features
n Ideal for low power/low noise 3.3V applications n Guaranteed simultaneous switching noise level and dynamic threshold performance n Guaranteed pin-to-pin skew AC performance n Guaranteed incident wave switching into 75
Ordering Code:
Order Number 74LVQ74SC 74LVQ74SJ Package Number M14A M14D Package Description 14-Lead (0.150" Wide) Molded Small Outline Integrated Circuit, SOIC JEDEC 14-Lead Molded Small Outline Package, SOIC EIAJ
Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
Logic Symbols
IEEE/IEC
DS011347-1 DS011347-3
Connection Diagram
Pin Assignment for SOIC JEDEC and EIAJ
DS011347-2
DS011347-4
(c) 1998 Fairchild Semiconductor Corporation
DS011347
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Pin Descriptions
Pin Names D1, D2 CP1, CP2 CD1, CD2 SD1, SD2 Q1, Q1, Q2, Q2 Description Data Inputs Clock Pulse Inputs Direct Clear Inputs Direct Set Inputs Outputs
Truth Table
Inputs SD L H L H H H CD H L L H H H CP X X X
N N
Outputs D X X X H L X Q H L H H L Q0 Q L H H L H Q0
L
H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial N = LOW-to-HIGH Clock Transition Q0(Q0) = Previous Q(Q) before LOW-to-HIGH Transition of Clock
Logic Diagram
DS011347-6
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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Absolute Maximum Ratings (Note 1)
Supply Voltage (VCC) DC Input Diode Current (IIK) VI = -0.5V VI = VCC + 0.5V DC Input Voltage (VI) DC Output Diode Current (IOK) VO = -0.5V VO = VCC + 0.5V DC Output Voltage (VO) DC Output Source or Sink Current (IO) DC VCC or Ground Current (ICC or IGND) Storage Temperature (TSTG) DC Latch-Up Source or Sink Current -0.5V to +7.0V -20 mA +20 mA -0.5V to VCC + 0.5V -20 mA +20 mA -0.5V to to VCC + 0.5V
Recommended Operating Conditions (Note 2)
Supply Voltage (VCC) Input Voltage (VI) Output Voltage (VO) Operating Temperature (TA) Minimum Input Edge Rate (V/t) VIN from 0.8V to 2.0V VCC @ 3.0V 2.0V to 3.6V 0V to VCC 0V to VCC -40C to +85C
125 mV/ns
50 mA 200 mA -65C to +150C 100 mA
Note 1: The "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteritics tables are not guaranteed at the absolute maximum ratings. The "Recommended Operating Conditions" table will define the conditions for actual device operation. Note 2: Unused inputs must be held HIGH or LOW. They may not float.
DC Electrical Characteristics
Symbol Parameter VCC (V) 3.0 3.0 3.0 3.0 3.0 3.0 3.6 3.6 3.6 3.6 3.3 3.3 3.3 3.3 0.2 -0.2 1.7 1.6 2.0 0.8 -0.8 2.0 0.8 0.002 TA = +25C Typ VIH VIL VOH Minimum High Level Maximum Low Level Input Voltage Minimum High Level Output Voltage 1.5 1.5 2.99 2.0 0.8 2.9 2.58 0.1 0.36 TA = -40C to +85C Guaranteed Limits 2.0 0.8 2.9 2.48 0.1 0.44 V V V V V V A mA mA A V V V V VOUT = 0.1V or VCC - 0.1V VOUT = 0.1V or VCC - 0.1V IOUT = -50 A VIN = VIL or VIH (Note 3) IOH = -12 mA VOL Maximum Low Level Output Voltage IOUT = 50 A VIN = VIL or VIH (Note 3) IOL = 12 mA IIN IOLD IOHD ICC VOLP VOLV VIHD VILD Maximum Input Leakage Current Minimum Dynamic (Note 4) Output Current Maximum Quiescent Supply Current Quiet Output Maximum Dynamic VOL Quiet Output Minimum Dynamic VOL Maximum High Level Dynamic Input Voltage Maximum Low Level Dynamic Input Voltage VI = VCC, GND VOLD = 0.8V Max (Note 5) VOHD = 2.0V Min (Note 5) VIN = VCC or GND (Notes 6, 7) (Notes 6, 7) (Notes 6, 8) (Notes 6, 8) Units Conditions
0.1
1.0
36 -25 20.0
Note 3: All outputs loaded; thresholds on input associated with output under test. Note 4: Maximum test duration 2.0 ms, one output loaded at a time. Note 5: Incident wave switching on transmission lines with impedances as low as 75 for commercial temperature range is guaranteed for 74LVQ. Note 6: Worst case package. Note 7: Max number of outputs defined as (n). Data inputs are driven 0V to 3.3V; one output at GND. Note 8: Max number of Data Inputs (n) switching. (n - 1) inputs switching 0V to 3.3V. Input-under-test switching: 3.3V to threshold (VILD), 0V to threshold (VIHD), f = 1 MHz.
3
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AC Electrical Characteristics
TA = +25C CL = 50 pF Min fmax tPLH tPHL tPLH tPHL tOSHL tOSLH Maximum Clock Frequency Propagation Delay CDn or SDn to Qn Propagation Delay CDn or SDn to Qn Propagation Delay CPn to Qn or Qn Propagation Delay CPn to Qn or Qn Output to Output Skew (Note 9) Data to Output 2.7 3.3 0.3 2.7 3.3 0.3 2.7 3.3 0.3 2.7 3.3 0.3 2.7 3.3 0.3 2.7 3.3 0.3 50 100 3.5 3.5 4.0 4.0 4.5 4.5 3.5 3.5 Typ 100 125 9.6 8.0 12.6 10.5 9.6 8.0 9.6 8.0 1.0 1.0 16.9 12.0 16.9 12.0 19.0 13.5 19.7 14.0 1.5 1.5 Max TA = -40C to +85C CL = 50 pF Min 40 95 3.5 2.5 3.5 3.5 4.0 4.0 3.5 3.5 19.0 13.0 19.0 13.5 23.0 16.0 21.0 14.5 1.5 1.5 ns ns ns ns ns Max MHz
Symbol
Parameter
VCC (V)
Units
Note 9: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH to LOW (tOSHL) or LOW to HIGH (tOSLH). Parameter guaranteed by design.
AC Operating Requirements
TA = +25C CL = 50 pF Typ tS tH tW trec Set-up Time, HIGH or LOW Hold Time, HIGH or LOW Dn to CPn Pulse Width Recovery Time 2.7 3.3 0.3 2.7 3.3 0.3 2.7 3.3 0.3 2.7 3.3 0.3 1.8 1.5 -2.4 -2.0 3.6 3.0 -3.0 -2.5 5.0 4.0 0.5 0.5 7.0 5.5 0 0 TA = -40C to +85C CL = 50 pF Guaranteed Minimum 6.5 4.5 0.5 0.5 10.0 7.0 0 0 ns ns ns ns
Symbol
Parameter
VCC (V)
Units
Capacitance
Symbol CIN CPD (Note 10)
Note 10: CPD is measured at 10 MHz.
Parameter Input Capacitance Power Dissipation Capacitance
Typ 4.5 25
Units pF pF
Conditions VCC = Open VCC = 3.3V
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Physical Dimensions
inches (millimeters) unless otherwise noted
14-Lead (0.150" Wide) Molded Small Outline Integrated Circuit, JEDEC (SC) Package Number M14A
5
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74LVQ74 Low Voltage Dual D-Type Positive Edge-Triggered Flip-Flop
Physical Dimensions
inches (millimeters) unless otherwise noted (Continued)
14-Lead Molded Small Outline Package, EIAJ (SJ) Package Number M14D
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Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.

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